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71410 sy 20100707-s00006 no.a1770-1/13 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LA72715NV overview jpn mts (multi channel television sound) decoder ic features ? with sif circuit, alignment-fr ee* stereo channel separation. * in base band signal input mode, separation is adjusted by input level. ? three i 2 c slave-addresses are prepared. ? the maximum output level is as large as 4.2dbv. (frequency = 1khz, distortion = less than 3%, v cc = 5v, typ) ? the external clock is unnecessary. ? a couple of external input terminal is prepared. functions ? stereo & bilingual demodulation. ? stereo & bilingual detection. ? just clock out. specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum power supply voltage v cc h max 7.0 v allowable power dissipation pd max ta 80 c, mounted on a specified board* 203 mw operating temperature topr -20 to +80 c storage temperature tstg -55 to +150 c * mounted on a specified board: 114.3mm 76.1mm 1.6mm glass epoxy board monolithic linear ic jpn mts (multi channel television sound) decoder ic orderin g numbe r : ena1770 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LA72715NV no.a1770-2/13 operating ranges at ta = 25 c parameter symbol conditions ratings unit recommended operating voltage v cc h 5.0 v allowable operating voltage v cc h op 4.5 to 5.5 v electrical characteristics at ta = 25 c, v dd = 5v [condition of input signal at pin 5] base band input [output] l-ch: pin 18, r-ch: pin 17 ratings parameter symbol conditions min typ max unit current dissipation i cc 1 no signal, inflow current at pin 19 18 26 34 ma -6 -4.5 -3 dbv mono output level v o mn1 fm = 1khz, 100% mod, pre-emphasis off 501 595 708 mvrms mono l/r level difference v o mn1 fm = 1khz, 100% mod, pre-emphasis off -1 0 1 db mono distortion thdm1 fm = 1khz, 100% mod, pre-emphasis off 0.2 0.5 % mono frequency charac teristics fcm1 fm = 10khz/1khz, 100% mod, 15khz lpf pre-emphasis off -18 -13.5 db mono s/n snm1 non mod, 15khz lpf 60 65 db -6 -4.5 -3 dbv stereo output level v o st1 fm = 1khz, 100% mod, cue (stereo), 15khz lpf 501 595 708 mvrms stereo distortion thds1 fm = 1khz, 100% mod, cue (stereo), 15khz lpf 0.5 1 % stereo s/n sns1 sub carrier (non mod), cue (stereo), 15khz lpf 50 60 db -6 -4.5 -3 dbv main output level v o ma1 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 501 595 708 mvrms main distortion thdma1 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 0.2 0.5 % main s/n snma1 sub carrier (non mod), cue (bilingual), 15khz lpf 60 65 db -6 -4.5 -3 dbv sub output level v o su1 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 501 595 708 mvrms sub distortion thdsu1 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 0.7 1.5 % sub frequency characte ristics fcsu1 fm = 10khz/1khz, 60% mod, cue (bilingual), 15khz lpf, pre-emphasis off -18 -14.5 db sub main s/n snsu1 sub carrier (non mod), cue (bilingual), 15khz lpf 50 60 db stereo separation l r sepr1 fm = 1khz (l-only), 60% mod, cue (stereo), 15khz lpf 35 43 db stero separation r l sepl1 fm = 1khz (r-only), 60% mod, cue (stereo), 15khz lpf 35 43 db stay behind carrier level (sub) clsu1 main = 0%, sub = 0% (carrier) cue (bilingual) -50 -40 dbv stay behind carrier level (main) clma1 main = 0%, sub = 0% (carrier) cue (bilingual) -55 -45 dbv cross-talk main sub ctsub1 main : fm = 1khz, 100% modulation, cue (bilingual), 1khz bpf 55 62 db cross-talk sub main ctma1 sub : fm = 1khz, 100% modulation, cue (bilingual), 1khz bpf 55 62 db mode output mono modmo1 input = mono signal 1.7 2 2.3 v mode output stereo modst1 input = stereo signal 0 1 1.3 v mode output bilingual modbi1 input = bilingual signal 2.7 3 3.3 v just clock output high voltage jch1 f = 400hz (mono), 25% mod 4 v just clock output low voltage jcl1 f = 400hz (mono), 10% mod 1 v 3.3 4.2 dbv max output level mol1 f = 1khz, distortion = 3% 1462 1622 mvrms continued on next page.
LA72715NV no.a1770-3/13 continued from preceding page. ratings parameter symbol conditions min typ max unit -14.5 dbv external input level extin1 f = 1khz, (pin 12 & pin 13 input) 188.4 mvrms 8pin-control ?h? muteh mute-on 3.0 v cc v 8pin-control ?open? muteop mute-off 0.9 v 8pin-control ?l? mutel mute-off & detection area conrol 0 0.2 v [condition of input signal at pin 5] deviation of sif input mono : (fm = 1khz) 100% 4.5mhz 25khz pre-emphasis on [output] l-ch : pin 18, r-ch : pin 17 ratings parameter symbol conditions min typ max unit current dissipation i cc 2 no signal, inflow current at pin 19 20 28 36 ma 70 90 110 db v input sensitivity level v s in fc = 4.5mhz 3.16 31.62 316.2 mvrms -6 -4.5 -3 dbv mono output level v o mn2 fm = 1khz, 100% mod, pre-emphasis off 501 595 708 mvrms mono l/r level difference v o mn2 fm = 1khz, 100% mod, pre-emphasis off -1 0 1 db mono distortion thdm2 fm = 1khz, 100% mod, pre-emphasis off 0.2 0.5 % mono frequency charac teristics fcm2 fm = 10khz/1khz, 100% mod, 15khz lpf pre-emphasis off -18 -13.5 db mono s/n snm2 non mod, 15khz lpf 55 60 db -6 -4.5 -3 dbv stereo output level v o st2 fm = 1khz, 100% mod, cue (stereo), 15khz lpf 501 595 708 mvrms stereo distortion thds2 fm = 1khz, 100% mod, cue (stereo), 15khz lpf 0.5 1 % stereo s/n sns2 sub carrier (non mod), cue (stereo), 15khz lpf 50 57 db -6 -4.5 -3 dbv main output level v o ma2 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 501 595 708 mvrms main distortion thdma2 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 0.2 0.5 % main s/n snma2 sub carrier (non mod), cue (bilingual), 15khz lpf 55 60 db -6 -4.5 -3 dbv sub output level v o su2 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 501 595 708 mvrms sub distortion thdsu2 fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 0.7 1.5 % sub frequency characte ristics fcsu2 fm = 10khz/1khz, 60% mod, cue (bilingual), 15khz lpf, pre-emphasis off -18 -14.5 db sub main s/n snsu2 sub carrier (non mod), cue (bilingual), 15khz lpf 50 58 db stereo separation l r sepr2 fm = 1khz (l-only), 60% mod, cue (stereo), 15khz lpf 35 38 db stero separation r l sepl2 fm = 1khz (r-only), 60% mod, cue (stereo), 15khz lpf 35 38 db stay behind carrier level (sub) clsu2 main = 0%, sub = 0% (carrier) cue (bilingual) -50 -40 dbv stay behind carrier level (main) clma2 main = 0%, sub = 0% (carrier) cue (bilingual) -55 -45 dbv cross-talk main sub ctsub2 main : fm = 1khz, 100% modulation, cue (bilingual), 1khz bpf 55 62 db cross-talk sub main ctma2 sub : fm = 1khz, 100% modulation, cue (bilingual), 1khz bpf 55 62 db mode output mono modmo2 input = mono signal 1.7 2 2.3 v mode output stereo modst2 input = stereo signal 0 1 1.3 v mode output bilingual modbi2 input = bilingual signal 2.7 3 3.3 v just clock output high voltage jch2 f = 400hz (mono), 25%mod 4 v continued on next page.
LA72715NV no.a1770-4/13 continued from preceding page. ratings parameter symbol conditions min typ max unit just clock output low voltage jcl2 f = 400hz (mono), 10%mod 1 v 3.3 4.2 dbv max output level mol2 f = 1khz, distortion = 3% 1462 1622 mvrms -14.5 dbv external input level extin2 f = 1khz, (pin 12 & pin 13 input) 188.4 mvrms 8pin-control ?h? muteh mute-on 3.0 v cc v 8pin-control ?open? muteop mute-off 0.9 v 8pin-control ?l? mutel mute-off & detection area conrol 0 0.2 v package dimensions unit : mm (typ) 3175c [LA72715NV] sanyo : ssop24(275mil) 7.8 5.6 7.6 0.22 0.65 (0.33) 12 13 24 1 0.5 0.15 1.5max 0.1 (1.3)
LA72715NV no.a1770-5/13 block diagram and test circuit 4.5mhz bpf i 2 c data mpx input base band mode application controlled by i 2 c n.c n.c. n.c. n.c. i 2 c clock test1 slave add select v cc 5v ext_in(r) mute h:mute open/l:normal v cc gnd ext_in(l) out(r) h:84h open:80h l:a0h + out(l) + + + 1 2 3 4 4 + 5 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 main sub cue det sub det logic control cue bpf 4.5fh trap 15khz lpf main deem just clk i 2 c decode 15khz lpf 3.5fh clk.g sub bpf sub deem sub demod comp regulator mode 952hz bpf am demod sif matrix sw lch rch amp(10db) slave address = 1000 000*b (16pin : open) slave address = 1000 010*b (16pin : h) slave address = 1010 000*b (16pin : l) + + audio analyzer + oscillo scope sg sif_input + sg dc volt meter
LA72715NV no.a1770-6/13 block diagram and application circuit example 1k 1k 100k sif_in from tuner match resistance (*2) 4.5mhz bpf just clk out (open collector) i 2 c data 10k mpx in base band mode application controlled by i 2 c n.c n.c. n.c. n.c. i 2 c clock test1 slave add select v cc 5v mode i/o ext_in(r) mute h:mute open/l:normal v cc gnd 1 f 4.7 f 0.1 f 0.01 f to 0.047 f (*1) 1 f ext_in(l) 1 f 4.7 f (*3) 1 f out(r) 2.2 f or more h:84h open:80h l:a0h + out(l) 2.2 f or more + 2.2 f + + 1 2 3 4 4 10 f + 5 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 main sub cue det sub det logic control cue bpf 4.5fh trap 15khz lpf main deem just clk i 2 c decode 15khz lpf 3.5fh clk.g sub bpf sub deem sub demod comp regulator mode 952hz bpf am demod sif matrix sw lch rch amp(10db) 0.1 f slave address = 1000 000*b (16pin : open) slave address = 1000 010*b (16pin : h) slave address = 1010 000*b (16pin : l) + 47 f 100 h r1 r2 (*2) 470k to 1m (*1) v cc the value of (1*), (2*), and (3*) affects sensitivity for si gnal detection. it must be adjusted depending on the circumstances by the user. (1*): recommended constant value 0.0033 f + 470k ? (values when tested) (2*): recommended matching resistor value r1=1k , r2=1k recommended bpf murata sfsra4m50df00-b0 (3*): recommended constant value 4.7 f to 10k the ceramic capacitor may be us ed for the electrolytic capacitor.
LA72715NV no.a1770-7/13 pin functions pin no. pin name dc voltage ac level function equivalent circuit 1 am detector dc : 2.3v reference terminal of am detection. 10k 10k v cc 1k 1k pad 2 14 dc filter out 2pin dc : 2.6v 14pin dc : 2.1v absorbing the dc offset of signal line by external capacity. pad 3 15 dc filter in dc : 2.4v absorbing the dc offset of signal line by external capacity. 2.4v 1k 2k 2k 100k pad 4 fm filter dc : 2.9v filter termi nal for making stable dc voltage of fm detection output in sif part. normally, use a condenser of 4.7 f. increase the capacity value with concerning frequency characteristics of low level. 1k 1k pad 5 sif input dc : 2.4v input terminal for sif. the input impedance is about 5k . be care for about pattern layout of the input circuit, because of causing buzz-beat and buzz by leaking noise signal into the input terminal. (the noise signal depending on sound is particularly video signal and chroma signal and so on. vif carrier becomes noise signal.) 10k 10k 500 500 pa d 6 gnd continued on next page.
LA72715NV no.a1770-8/13 continued from preceding page. pin no. pin name dc voltage ac level function equivalent circuit 7 just clock out 5v 0v rectangle wave output for just clock. (open collector) 100k pull-up 5k pad 8 mute control pin & distinction control. dc : 0v 3.0v to v cc : mute (cont 1) open (0.9v) : norm 0v : norm & detection area control (cont2) use it within the range of 0 to 0.2v when you operate usually. 2.4v reg pad cont2 cont1 9 serial data input pin. 0v 5v high : 2.5v to 5v low : 0v to 1.5v 500 30 a pad 10 serial clk input pin 0v 5v high : 2.5v to 5v low : 0v to 1.5v 500 30 a pad 11 test1 12 extin_r dc : 2.4v -14.5dbv ext input rch not used : open 2.4v 50k v cc 1k pad 13 extin_l dc : 2.4v -14.5dbv ext input lch not used : open 2.4v 50k v cc 1k pad continued on next page.
LA72715NV no.a1770-9/13 continued from preceding page. pin no. pin name dc voltage ac level function equivalent circuit 16 slave add select 17 18 line out (r) terminal line out (l) terminal dc : 2.4v ac : -4.5dbv line output pin. 250 300 50k 50k 2.5pf 2.5pf pa d 19 v cc 5v 20 mts mode out no signal dc : 2.0v detection output for m.t.s. signal. bilingual :3.0v mono :2.0v stereo :1.0v 10k 10k pad 21 reg filt dc : 2.4v filter terminal of reference voltage source 10k 10k 10k 500 50k 500 pad 22 23 24 nc i 2 c bus serial interface specification (1) data transfer manual this lsi adopts control method (i 2 c-bus) with serial data, and contro lled by two terminals which called scl (serial clock) and sda (seria l data). at first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to sda terminal with synchronized scl terminal clock. the order of transf erring is first, msb (the most scale of bit), and save the order. the 9th bit takes ack (acknow ledge) period, during scl terminal takes ?h?, this lsi pull down the sda terminal. after tr ansferred the necessary data, two te rminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 defined by scl rise down sda during ?h? period. *2 defined by scl rise up sda during ?h? period. (2) transfer data format after transfer start condition, transfers slave address (1000 000 * ) to sda terminal, control data, then, stop condition (see figure 1). slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, if it is ?l? takes write mode (as this lsi side, this is input operation mode), and in case of ?h? reading mode (as this lsi side, this is output operation mode). data works with all of bit, transfer the stop condition before stop 8bit transf er, and to stop transfer, it will be canceled the transfer dates. at read mode, this lsi outputs during ack period, please must input 9 clocks. *3 it is called r/w bit.
LA72715NV no.a1770-10/13 fig.1 data structure ?write? mode start condition slave address r/w l ack control data ack stop condition fig.2 data structure ?read? mode start condition slave address r/w h ack internal data * ack stop condition ? the output data synchronizes with the clock of scl pin. then the ack output is made after the output data. bit8 is result of stero det (h : stereo) bit7 is result of biling ual det (h : bilingual) bit6 is initial condition ?h? bit5 to bit1 are fixed to ?l? (3) initialize this ic is initialized for circuit protection. initial condition is ?01h (main-mode) ?. reference parameter symbol min max unit low level input voltage v il -0.5 1.5 v high level input voltage v ih 2.5 5.5 v low level output current i ol 3.0 ma scl clock frequency f scl 0 100 khz set-up time for a repeated start condition t su : sta 4.7 s hold time start condition. after this peri od, the first clock pulse is generated t hd : sta 4.0 s low period of the scl clock t low 4.7 s rise time of both sda and sdl signals t r 0 1.0 s high period of the scl clock t high 4.0 s fall time of both sda and sdl signals t f 0 1.0 s data hold time t hd : dat 0 s data set-up time t su : dat 250 ns set-up time for stop condition t su : sto 4.0 s bus free time between a stop and start condition t buf 4.7 s definition of timing t hd:sta t su:sta t low t r t f t high t hd:data t su:dat t su:sto t buf scl sda
LA72715NV no.a1770-11/13 i 2 c control/LA72715NV group number is only 1 (normal use). grp-1 d8 d7 d6 d5 d4 d3 d2 d1 condition 0 0 bilingual * 0 1 main 1 0 sub 1 1 (prohibit) * 0 normal 1 forced mono * 0 normal (mute off) 1 mute * 0 tv mode (sw normal) 1 ext mode (sw ext) * 0 just clock off 1 just clock on * 0 sif mode 1 base band mode * 0 fix 1 prohibit (test mode) *: initial condition read out data d8 d7 d6 d5 d4 d3 d2 d1 condition 0 0 0 0 0 fixed 0 normal 1 stereo det 0 normal 1 bilingual det 0 except an initial condition 1 initial condition test mode condition when stop condition transform at grp-1 data-end, controlled normal mode. grp-2 (only test condition : normally, this group is hidden group) d8 d7 d6 d5 d4 d3 d2 d1 condition/moniter position 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 1 test-01 sif out 0 0 0 0 0 0 1 0 test-02 sub fil out 0 0 0 0 0 0 1 1 test-03 cue fil out 0 0 0 0 0 1 0 0 test-04 sud det out 0 0 0 0 0 1 0 1 test-05 cue dc1 out 0 0 0 0 0 1 1 0 test-06 sub det2 out 0 0 0 0 0 1 1 1 test-07 110k out 0 0 0 0 1 0 0 0 test-08 28k out 0 0 0 0 1 0 0 1 test-09 cue pls out 0 0 0 0 1 0 1 0 test-10 fil zap level slave address 80h (16pin : open) slave address 84h (16pin : v cc ) slave address a0h (16pin : gnd)
LA72715NV no.a1770-12/13 mode select (pin & i 2 c setting) mute pin setting i 2 c output mode read mode out mode i/o broadcast signal 8pin d5 d4 d3 d2 d1 lch (18pin) rch (17pin) mode d8 d7 20pin l or open 0 0 0 0 0 main sub both 0 1 l or open 0 0 0 0 1 main main main 0 1 l or open 0 0 0 1 0 sub sub sub 0 1 l or open 0 0 1 * * main main mono 0 1 * * 1 * * * mute mute mute 0 1 h * * * * * mute mute mute 0 1 bilingual l or open 1 0 * * * ext l ext r ext 0 1 3v l or open 0 0 0 * * l r stereo 1 0 l or open 0 0 1 * * l+r l+r mono 1 0 * * 1 * * * mute mute mute 1 0 h * * * * * mute mute mute 1 0 stereo l or open 1 0 * * * ext l ext r ext 1 0 1v l or open 0 0 * * * l+r l+r mono 0 0 * * 1 * * * mute mute mute 0 0 h * * * * * mute mute mute 0 0 mono l or open 1 0 * * * ext l ext r ext 0 0 2v 16pin : slave address select. 0v to 1.5v : a0h, open : 80h, 3.0v to v cc : 84h serial data specification (i 2 c bus communication) data bit msb lsb d8 d7 d6 d5 d4 d3 d2 d1 test sif or base band just clk ext source select normal out mute forced mono bilingual mode select 0 : off 1 : on 0 : sif 1 : base band 0 : off 1 : on 0 : off(tv) 1 : ext 0 : off 1 : on 0 : off 1 : on 00:bilingual 01 : main 10 : sub 11 : unusable note : underline shows default setting
LA72715NV ps no.a1770-13/13 frequency, f ? khz output frequency characteristics typ (30%mod sif_in) ? 10 ? 8 ? 6 ? 4 ? 2 0 2 4 500 1000 1500 6 ? 10 ? 5 0 5 10 0.01 1 0.1 2 3 57 2 3 57 2 3 57 10 1 23 57 23 57 23 57 0.1 10 300 200 100 output level ? db main degree of modulation ? % main degree of modulation ? output level & distortion factor typ (1khz sif_in) 0 2000 1 2 3 0 4 0 output level ? mvrms distortion factor ? % frequency, f ? khz de-emphasis characteristics typ (30%mod sif_in) ? 15 0.01 output level ? db main st_lch st_rch sub main sub output level distortion factor LA72715NV reference characteristics on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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